Error: Can't synthesize current design -- Top partition does not contain any logic

Thanks Pletz,

Atlast I did my required project with the code below, thanks a lot for your help.

//Verilog HDL code for intelligent Traffic system with 7seg display properties:

module traffic1(R, G, Y, pm, clock, reset,seg7);

output R, Y, G; // Red, Yellow, Green Signal lines

input clock, reset, pm;

reg R, Y, G;

output [6:0]seg7; // 7bit is output signal

reg [6:0]seg7; // Define 7bit register

//state machine parameters

reg [1:0] present_state, next_state;

parameter Green = 2'b00,

Yellow = 2'b01,

Red = 2'b10,

Reset_State = 2'b11;

// clock divider

reg [27:0] divider;

reg [24:0] divider1;

reg reg1;

reg temp;

wire enable_state;

// counter as clock divider

always @(posedge clock) begin

if (reset) divider <= 0 ;

else divider <= divider + 1;

if (reset) divider1 <= 0;

else divider1 <= divider1 + 1;

end

always @(posedge clock) begin

if (reset) reg1 <= 0;

else if (pm) reg1<= divider1[24];

else reg1 <= divider[27];

end

// edge detector for counter bit [3]

// Needed to make the enable signal one clock cycle long

always @(posedge clock) begin

if (pm) temp <= divider1[24]& !reg1;

else

temp <= divider[27]& !reg1;

end

assign enable_state = temp;

// End clock divider

always @ (posedge clock)

begin

if(reset)

present_state = Reset_State;

else if (enable_state)

present_state = next_state;

end

always @ (present_state)

case (present_state)

Green:

begin

G = 1'b1;

R = 1'b0;

//Y = 1'b0;

next_state = Yellow;

end

Yellow:

begin

Y = 1'b1;

G = 1'b0;

//R = 1'b0;

next_state = Red;

end

Red:

begin

R = 1'b1;

Y = 1'b0;

//G = 1'b0;

next_state = Green;

end

Reset_State:

begin

R = 1'b0;

Y = 1'b0;

G = 1'b0;

next_state = Red;

end

endcase

always @(pm)

begin

case(pm) // flollw operation of a

1'b1 : seg7 = 7'b0001000; //A

default : seg7 = 7'b0001100; //P

endcase

end

endmodule