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Altera_Forum
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18 years ago

Error: Can't synthesize current design -- Top partition does not contain any logic

Dear Sir, I am trying one code for verilog traffic signal controller, but it seems the above error? would you please tell me how to solve this?? the code is below: module traffic; param...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Dear Sir,

Thanks for your reply.

to see the changing effect on DE2 board, is that okey if I increase delay with# 1000??

or what else, I can do if I want to see the change?

sincerely

Kazi Mamun