Erratic ring counter

Question

I have built a ring counter using D flip flops in an EMP3128ATC100-10 cpld. I am getting erratic results with clocking sometimes occurring on both rising and falling edges and sometimes no clocking at all. Also some flip flops are seen to clock at the wrong clock instance. I've attached my schematic and a logic analyser display showing the erratic clocking. Anyone got any ideas why this behaviour? Note that the reset line was taken low then returned high several mSec before applying the clock.

altera_forum · Answer

Since FCLK is excrutiatingly slow on the logic analyser trace, can you guarantee clean monotonic rise and fall of the clock with a few nanoseconds or less rise and fall times?

[It's been a long time since I've seen a CPLD schematic. Makes me nostalgic for the early '90s.]

Sinc CPLDs have clean, wide inputs you might want to consider changing the least significant bit from a feedback of the most significant bit to a detect of all but the last bit being zero. This would provide recovery in case of a bad clock or other problematic event but could mask problems like what you're seeing. If you end up with more than one bit asserted, they'll shift out untill the bits are (mostly) deassered and start you fresh with one and only one assertion. If your single bit gets dropped mid-stream, a new one will start over when there is none to be seen.

altera_forum · Answer

My FCLK is derived from a AD9833 direct digital synthesis chip, it appears to have a rise time of about 1uSec. Would you suggest I include circuitry to speed up the rise time?

Thanks for the idea of using a decoded signal to set the D input of FF1. I'll give that a closer look and also hope I have enough macrocells left, I'm currently running at 98% usage.

altera_forum · Answer

You should be able to reconfigure the AD9833 for digital quality risetimes using the DAC data MSB or DAC data MSB/2 modes.  I'm pretty sure the problem you're having is with the much longer than acceptable rise time (40 ns per the Altera CPLD data sheet) causing non-monotonicity due to internal or external noise at threshold.

altera_forum · Answer

Thanks for your ideas. I'll research the AD9833 a little further to see what I can do to improve the rise times. I really think you hit the nail on the head suggesting I look at the rise time. The rest of the CPLD contains the address decoding, output latching etc. for 5 I2C slave devices and that all works fine so bad clocking due to slow rise time sounds most likely.

altera_forum · Answer

The most effective way to convert a signal with slow edges into a clean digital clock is a schmitt-trigger respectively a comparator with hysteresis.

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Erratic ring counter

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