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Altera_Forum's avatar
Altera_Forum
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14 years ago

Erratic ring counter

I have built a ring counter using D flip flops in an EMP3128ATC100-10 cpld. I am getting erratic results with clocking sometimes occurring on both rising and falling edges and sometimes no clocking a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for your ideas. I'll research the AD9833 a little further to see what I can do to improve the rise times. I really think you hit the nail on the head suggesting I look at the rise time. The rest of the CPLD contains the address decoding, output latching etc. for 5 I2C slave devices and that all works fine so bad clocking due to slow rise time sounds most likely.