Erratic ring counter

Since FCLK is excrutiatingly slow on the logic analyser trace, can you guarantee clean monotonic rise and fall of the clock with a few nanoseconds or less rise and fall times?

[It's been a long time since I've seen a CPLD schematic. Makes me nostalgic for the early '90s.]

Sinc CPLDs have clean, wide inputs you might want to consider changing the least significant bit from a feedback of the most significant bit to a detect of all but the last bit being zero. This would provide recovery in case of a bad clock or other problematic event but could mask problems like what you're seeing. If you end up with more than one bit asserted, they'll shift out untill the bits are (mostly) deassered and start you fresh with one and only one assertion. If your single bit gets dropped mid-stream, a new one will start over when there is none to be seen.