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Altera_Forum's avatar
Altera_Forum
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14 years ago

Erratic ring counter

I have built a ring counter using D flip flops in an EMP3128ATC100-10 cpld. I am getting erratic results with clocking sometimes occurring on both rising and falling edges and sometimes no clocking a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You should be able to reconfigure the AD9833 for digital quality risetimes using the DAC data MSB or DAC data MSB/2 modes. I'm pretty sure the problem you're having is with the much longer than acceptable rise time (40 ns per the Altera CPLD data sheet) causing non-monotonicity due to internal or external noise at threshold.