Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Erratic ring counter

I have built a ring counter using D flip flops in an EMP3128ATC100-10 cpld. I am getting erratic results with clocking sometimes occurring on both rising and falling edges and sometimes no clocking a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

My FCLK is derived from a AD9833 direct digital synthesis chip, it appears to have a rise time of about 1uSec. Would you suggest I include circuitry to speed up the rise time?

Thanks for the idea of using a decoded signal to set the D input of FF1. I'll give that a closer look and also hope I have enough macrocells left, I'm currently running at 98% usage.