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New ContributorDoes direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?
Hi all,
I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR.
I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？
The issue has been resolved. The root cause was that parameters from the upstream module were not propagated correctly, which caused this specific Master path to be optimized away during synthesis. Thank you all for your suggestions
10 Replies
sstrellSuper Contributor
Yes, this is how it should work.
Be sure to check the addressing for both of those AXI managers on the Address Map tab to make sure the EMIF is at the address location you want, especially if it should be different for the two managers.
wangduoyuThanks. Is it necessary to use an AXI Bridge to solve the addressing issue? Currently, my custom defined AXI Master shows no options in the Address Map tab, even after I connect it to the DDR in the System View
- sstrell
What are you seeing on the Address Map tab? You have to select the manager from the list on the left to see its address map. Every host/manager has its own address map.
yukiOccasional Contributor
This is helpful.
