Forum Discussion
wangduoyu
New Contributor
New ContributorDoes direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply conn...
The issue has been resolved. The root cause was that parameters from the upstream module were not propagated correctly, which caused this specific Master path to be optimized away during synthesis. Thank you all for your suggestions
AdzimZM_Altera
Regular Contributor
Regular ContributorHi wangduoyu,
What type of synthesis away warning you got?
Did you run the read and write test with AXI_master1?
Maybe you can add attribute "/* synthesis preserve */" to the register?
Regards,
Adzim
wangduoyuNew Contributor
New ContributorThe issue has been resolved. The root cause was that parameters from the upstream module were not propagated correctly, which caused this specific Master path to be optimized away during synthesis. Thank you all for your suggestions
