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wangduoyu's avatar
wangduoyu
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5 months ago
Solved

Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?

Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply conn...
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Core Logic
  • wangduoyu's avatar
    wangduoyu
    5 months ago

    The issue has been resolved. The root cause was that parameters from the upstream module were not propagated correctly, which caused this specific Master path to be optimized away during synthesis. Thank you all for your suggestions

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 months ago

Yes, this is how it should work.

Be sure to check the addressing for both of those AXI managers on the Address Map tab to make sure the EMIF is at the address location you want, especially if it should be different for the two managers.

wangduoyu's avatar
wangduoyu
Icon for New Contributor rankNew Contributor
5 months ago

Thanks. Is it necessary to use an AXI Bridge to solve the addressing issue? Currently, my custom defined AXI Master shows no options in the Address Map tab, even after I connect it to the DDR in the System View