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wangduoyu's avatar
wangduoyu
Icon for New Contributor rankNew Contributor
2 months ago
Solved

Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?

Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply conn...
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Core Logic
  • wangduoyu's avatar
    wangduoyu
    2 months ago

    The issue has been resolved. The root cause was that parameters from the upstream module were not propagated correctly, which caused this specific Master path to be optimized away during synthesis. Thank you all for your suggestions

yuki's avatar
yuki
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

This is helpful.