Forum Discussion
New ContributorDebugging the FPGAs connected in passive serial mode
I have two cyclone 3 devices(EP3C16F484C8 & EP3C5F256C8) which is connected in passive serial mode. I wanted to debug the device and only JTAG connection is available to do so. I don't want to change anything in the code and i don't want to reprogram, I don't want to use signal tap either. How can i debug the devices while the device is running? My device frequency is 26 mHz, but most of my outputs changes 10 times in 15s but it is ruled by 26 MHz frequency
11 Replies
FvMSuper Contributor
Hi
JTAG interface is always available independent of selected configuration mode.
If you don't want to modify your design by inserting debug IP, e.g. Signal Tap, boundary scan is the only way to observe or optionally modify FPGA signals. EP3C16 scan chain length is 1080, EPEC5 603. Respectively IO scan speed is limited to a few kHz, depending on capabilities of boundary scan tool and JTAG interface speed. Maximum JTAG speed handled by EP3C is 25 MHz.
Regards Frank
AnnuI know the JTAG boundary scan is slow can we use VJTAG for this. If yes, how is it done? and also any manual for JTAG boundary scan is available
- FvM
Hi,
VJTAG involves changing your design, said you don't want to. If VJTAG is an option, why not Signal Tap?
Boundary-Scan Testing is briefly described in a Cyclone III Device Handbook chapter.
Regards
Frank
- FvM
See below waveform recorded with TopJTAG tool on CY1000 Cyclone 10 eval board:
- Annu
Can we do the boundary scan using the Quartus II programmer only or do we need external software for the scan.
JohnT_AlteraRegular Contributor
Unfortunately you will need to use external software to do it.
- sstrell
If you don't want to change the design, I'd recommend either copying the project or using the Revisions feature in Quartus. This way you can create a new revision, add Signal Tap or something else without changing the rest of the design, compile and debug, and then quickly go back to the original design as if nothing changed.
