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Annu's avatar
Annu
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3 months ago

Debugging the FPGAs connected in passive serial mode

I have two cyclone 3 devices(EP3C16F484C8 & EP3C5F256C8) which is connected in passive serial mode. I wanted to debug the device and only JTAG connection is available to do so. I don't want to change...
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Core Logic
Programmable Logic Device
Annu's avatar
Annu
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3 months ago

I know the JTAG boundary scan is slow can we use VJTAG for this. If yes, how is it done? and also any manual for JTAG boundary scan is available

FvM's avatar
FvM
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3 months ago

Hi,
VJTAG involves changing your design, said you don't want to. If VJTAG is an option, why not Signal Tap?

Boundary-Scan Testing is briefly described in a Cyclone III Device Handbook chapter.

Regards
Frank