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Annu's avatar
Annu
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1 month ago

Debugging the FPGAs connected in passive serial mode

I have two cyclone 3 devices(EP3C16F484C8 & EP3C5F256C8) which is connected in passive serial mode. I wanted to debug the device and only JTAG connection is available to do so. I don't want to change...
Configuration
Core Logic
Programmable Logic Device
FvM's avatar
FvM
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1 month ago

Hi

JTAG interface is always available independent of selected configuration mode.

If you don't want to modify your design by inserting debug IP, e.g. Signal Tap, boundary scan is the only way to observe or optionally modify FPGA signals. EP3C16 scan chain length is 1080, EPEC5 603. Respectively IO scan speed is limited to a few kHz, depending on capabilities of boundary scan tool and JTAG interface speed. Maximum JTAG speed handled by EP3C is 25 MHz.

Regards Frank

  • Annu's avatar
    Annu
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    1 month ago

    I know the JTAG boundary scan is slow can we use VJTAG for this. If yes, how is it done? and also any manual for JTAG boundary scan is available

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      1 month ago

      Hi,
      VJTAG involves changing your design, said you don't want to. If VJTAG is an option, why not Signal Tap?

      Boundary-Scan Testing is briefly described in a Cyclone III Device Handbook chapter.

      Regards
      Frank 

    • JohnT_Altera's avatar
      JohnT_Altera
      Icon for Regular Contributor rankRegular Contributor
      1 month ago

      For internal core issue, SignalTap will be the best solution. For Boundary Scan, you can only debug interface pin issue and the detection will be very slow and not efficient for interface pin that keep on toggling.