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Yassine-Ca's avatar
Yassine-Ca
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1 year ago

DE1 Cyclone V Verilog

Hello,

I create a small project using Quartus and Platform Designer.

In Platform Designer, I create NIOS II, On-Chip memory, JTAG UART and FIFO Avalon memory, I intrconnect them then I have generated Verilog , please see image below.

When I try to compile over Quartus, I get this error : Error (12002): Port "avalonmm_read_slave_read" does not exist in macrofunction "nios2_memory" , I know that it means that there is no signal in this name.

My question is, where are located the generated port signals ( Read from memory, write to memory) from generated by Platfom Designer, I found just clock signal and reset signal.

Please find attached the generated files by Platform Designer.

Thank you

Board Debug

17 Replies

  • sstrell's avatar
    sstrell
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    1 year ago

    The _inst.v file is just an instantiation template for instantiated the PD system in an upper-level design file in Quartus. It only lists the exported interfaces, which in your case are just clock and reset.

    If you are using this system as your top-level design in your Quartus project, set the top-level entity name in Quartus to NIOS2_memory_JTAG and add the .qsys file to your project. Regenerate the system in PD and then recompile in Quartus.

    • Yassine-Ca's avatar
      Yassine-Ca
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      1 year ago

      Hi,

      Thank you for your reply.

      I use another file as my top-level, and i declare the NIOS2_memory_JTAG inside it.

      Because I have the addresses of FIFO in, out and csr, on chip , nios2 debug memory slave, Can I just use these with bus address to write data to the FIFO memory.

      Regards.

      • sstrell's avatar
        sstrell
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        1 year ago

        You mean in your code for the processor? Sure. But you can find all the macros in the generated system.h file from PD.

        Side note: I don't know what version of Quartus you are using, but it's not recommended to start new designs with Nios II since it's been obsoleted by Nios V.

    • Yassine-Ca's avatar
      Yassine-Ca
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      1 year ago

      Hi,

      Sorry It was a mistake sending that reply in this page.

      From Quartus I try to open NIOS 2 software build tool to generate BSP but no way.

      What do you suggest, is the quartus version standard is not working for this?.

      Best regards.

    • Yassine-Ca's avatar
      Yassine-Ca
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      1 year ago

      Hi,

      Have you the link to download the version?.

      Regards.

      • Yassine-Ca's avatar
        Yassine-Ca
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        1 year ago

        Hi,

        I installed eclipse, now it's OK.

        I will procced to BSP files.

        Regards.

  • RichardT_altera's avatar
    RichardT_altera
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    1 year ago

    I believe sstrell has answered your inquiry.

    Do you need further help regarding this case?

    Regards,

    Richard Tan

    • Yassine-Ca's avatar
      Yassine-Ca
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      1 year ago

      Hi Richard,

      Thank you for your support.

      I'm using Quartus 23.1, I have issue with Eclipse for NIOS II with elf file not existing.

      I browse the Nios II Handbook, I found that the latest version of Quartus is 21.3

      Can I get a problem of incompatibility.

      Regards.

      • Yassine-Ca's avatar
        Yassine-Ca
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        1 year ago

        Hi,

        In the NIOS II new book, there is compatibility.

        The problem was in the template in Eclipse, when I changed it to Helloworld small, the ELF file is generated.

        I got these warnings on the Quartus:

        Warning (10036): Verilog HDL or VHDL warning at seven_segment_display.v(18): object "display_data" assigned a value but never read
        Info (12128): Elaborating entity "seven_segment_decoder" for hierarchy "seven_segment_decoder:temp_tens_decoder"
        Warning (10036):............................

        To share the solution with you: I just added the module that declare the system components (NIOS 2+On Chip Memory + FIFO + JTAG) in the top level module declaration with the qip file added to the project.

        Here the declaration inside top level,according to my project :

        temp_hum u_rdwr (
        .clk_clk(clk),
        );

        Regards.

        Yassine

  • RichardT_altera's avatar
    RichardT_altera
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    1 year ago

    I believe your follow-up question is related to Nios II, which unfortunately is not within my area of expertise.

    Could you please raise a separate case for your follow-up technical problem, and an agent will be assigned to your case?

    At Altera, we prefer a new case for each unique technical problem, as it aids our case analysis and helps us assess our customer support requirements.

    Thank you for your understanding.

    Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Regards,

    Richard Tan

    • Yassine-Ca's avatar
      Yassine-Ca
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      1 year ago

      Hello,

      The link is not working.

      Regards.