Forum Discussion
New ContributorDE1 Cyclone V Verilog
New ContributorHi,
Thank you for your reply.
I use another file as my top-level, and i declare the NIOS2_memory_JTAG inside it.
Because I have the addresses of FIFO in, out and csr, on chip , nios2 debug memory slave, Can I just use these with bus address to write data to the FIFO memory.
Regards.
Super ContributorYou mean in your code for the processor? Sure. But you can find all the macros in the generated system.h file from PD.
Side note: I don't know what version of Quartus you are using, but it's not recommended to start new designs with Nios II since it's been obsoleted by Nios V.
- Yassine-Ca
Hi,
My FPGA is DE1 and the quartus prime version 23.1 std.
My top-level file is used to display retreived data from FIFO memory into 7-segments.
I serached for the system.h file but not found in project folders, where can I find it, as i mentioned the NIOS2 files was generated by Platform Designer Qsys.
Is the DE1 supports Nios V, if Yes I can start a new design.
Regards.
- sstrell
Sorry, I forgot you have to generate the BSP (board support package) first to create the system.h file.
Nios V is supported in all devices that supported Nios II (as long as you have device resources available to implement it of course).
- Yassine-Ca
Hi,
In the BSP file just for Clk and reset.
I'm searching now macros for intel in this link, is This can help?
Regards.
