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New ContributorDE1 Cyclone V Verilog
Super ContributorThe _inst.v file is just an instantiation template for instantiated the PD system in an upper-level design file in Quartus. It only lists the exported interfaces, which in your case are just clock and reset.
If you are using this system as your top-level design in your Quartus project, set the top-level entity name in Quartus to NIOS2_memory_JTAG and add the .qsys file to your project. Regenerate the system in PD and then recompile in Quartus.
Yassine-CaHi,
Thank you for your reply.
I use another file as my top-level, and i declare the NIOS2_memory_JTAG inside it.
Because I have the addresses of FIFO in, out and csr, on chip , nios2 debug memory slave, Can I just use these with bus address to write data to the FIFO memory.
Regards.
- sstrell
You mean in your code for the processor? Sure. But you can find all the macros in the generated system.h file from PD.
Side note: I don't know what version of Quartus you are using, but it's not recommended to start new designs with Nios II since it's been obsoleted by Nios V.
- Yassine-Ca
Hi,
My FPGA is DE1 and the quartus prime version 23.1 std.
My top-level file is used to display retreived data from FIFO memory into 7-segments.
I serached for the system.h file but not found in project folders, where can I find it, as i mentioned the NIOS2 files was generated by Platform Designer Qsys.
Is the DE1 supports Nios V, if Yes I can start a new design.
Regards.
