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Yassine-Ca
New Contributor
New ContributorDE1 Cyclone V Verilog
Hello, I create a small project using Quartus and Platform Designer. In Platform Designer, I create NIOS II, On-Chip memory, JTAG UART and FIFO Avalon memory, I intrconnect them then I have genera...
sstrell
Super Contributor
Super ContributorHuh? No, that document has nothing to do with this. See this training: https://learning.intel.com/Developer/learn/courses/14714/niosr-v-software-development-flow-with-ashling-riscfree-ide-for-intelr-fpga
Yassine-CaNew Contributor
New ContributorHi,
Sorry It was a mistake sending that reply in this page.
From Quartus I try to open NIOS 2 software build tool to generate BSP but no way.
What do you suggest, is the quartus version standard is not working for this?.
Best regards.
