DDR3 HMC settings

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I am now working to use two 16bits DDR3 to get a 32bits data width DDR3, my question is how will i to do with the settings of "Number of chip selects" and "Mirror Addressing:1 per chip select" ?

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Typically you select the 16-bit memory IC from the right-side of the GUI and click "Apply", and then under the "Memory Parameters" tab change the width from 16-bits to 32-bits.

Cheers,

Dave

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Typically you select the 16-bit memory IC from the right-side of the GUI and click "Apply", and then under the "Memory Parameters" tab change the width from 16-bits to 32-bits.

Cheers,

Dave

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Hi,

Thanks.

Do you mean that let the settings of "Number of chip selects" and "Mirror Addressing:1 per chip select" to be default?

Best Regards!

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Do you mean that let the settings of "Number of chip selects" and "Mirror Addressing:1 per chip select" to be default?

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Right.

Do you have a schematic for your board? Or are you designing a board? If you look at your schematic, it likely only has a single chip-select. If your design has the 32-bit bus made from two 16-bit devices, then the chip select, control codes, and address signals are all common (and terminated to Vtt) for the two DDR devices.

Cheers,

Dave

Hi,

I am glad to get your reply.I am planning to design a board using Cyclone V with 32bits DDR3 (two 16bits DDR3s) connected to one hard memory controller.

Thank you very much!

ZCS

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I am planning to design a board using Cyclone V with 32bits DDR3 (two 16bits DDR3s) connected to one hard memory controller.

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In that case, look at the schematics for some of the Altera Cyclone V development boards. There's no need to buy them, just download and install their development kits, and then look at their schematics and PCB layout.

Cheers,

Dave

Thank you very much! I have download the development kits of Cyclone V.

Now I have another question and sorry to disturb you.

when i do clock design of Cyclone V 5CEFA9F31, should i use one clock to drive the all FPGA with two DDR3 HMCs or drive each bank by distributed clock coming through dedicated pins of each bank?

which way is better?

Best Regards!

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when i do clock design of Cyclone V 5CEFA9F31, should i use one clock to drive the all FPGA with two DDR3 HMCs or drive each bank by distributed clock coming through dedicated pins of each bank?

which way is better?

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You'll need to synthesize the design and see. Because the DDR interface uses a PLL, the solution likely involves using a PLL clock input on the same side of the device as the DDR interface. If the two DDR interfaces are on the same side of the device, then you can use PLL+DLL sharing (its an option in the DDR UniPHY setup).

Cheers,

Dave

Thank you Dave,

Do you mean that there is no restriction on the source of pll_ref_clk of the DDR3 hard controller,in other words,the pll_ref_clk can be driven by the clock in FPGA,not must be driven by the clock from the dedicated clock input pins?

Best Regards!

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Do you mean that there is no restriction on the source of pll_ref_clk of the DDR3 hard controller,in other words,the pll_ref_clk can be driven by the clock in FPGA,not must be driven by the clock from the dedicated clock input pins?

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There *ARE* restrictions on the clock input pin (it needs to be a PLL clock input), and there *ARE* further restrictions on the interface actually meeting timing. You need to synthesize a design using Quartus to determine how to meet those requirements. Yes, this takes a little "guesswork", but in general, start with a single DDR controller with a PLL clock input on the same side as the DDR controller pins. If that meets timing, then you have your "golden reference". From that, you can start to change the PLL input clock and see what warnings Quartus generates.

Cheers,

Dave

Hi,Dave

I have some questions and hope you can help me.

1.How to understand the statement "Connect unused pins as defined in the Quartus II software" in Cyclone V Device Family Pin Connection Guidelines?

2.Does the dedicated clock input pins use the BANK supplies where they are located? I now connect the LVDS(2.5V) clock to the clock input pins of the bank with 1.5v bank supply for DDR3, I am not sure whether this is correct.

Best Regards