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when i do clock design of Cyclone V 5CEFA9F31, should i use one clock to drive the all FPGA with two DDR3 HMCs or drive each bank by distributed clock coming through dedicated pins of each bank?
which way is better?
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You'll need to synthesize the design and see. Because the DDR interface uses a PLL, the solution likely involves using a PLL clock input on the same side of the device as the DDR interface. If the two DDR interfaces are on the same side of the device, then you can use PLL+DLL sharing (its an option in the DDR UniPHY setup).
Cheers,
Dave
Honored Contributor
