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Honored Contributor
Honored ContributorDDR3 HMC settings
Hi, all I am now working to use two 16bits DDR3 to get a 32bits data width DDR3, my question is how will i to do with the settings of "Number of chip selects" and "Mirror Addressing:1 per chip ...
Altera_ForumHonored Contributor
Honored ContributorThank you Dave,
Do you mean that there is no restriction on the source of pll_ref_clk of the DDR3 hard controller,in other words,the pll_ref_clk can be driven by the clock in FPGA,not must be driven by the clock from the dedicated clock input pins? Best Regards!
