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1.How to understand the statement "Connect unused pins as defined in the Quartus II software" in Cyclone V Device Family Pin Connection Guidelines?
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You read notes 12 and 13 as the PCG file recommends, and then you scratch your head and wonder what it means :)
The *best* way to make sure all synthesis "rules" are followed is to create your top-level design, and use Quartus to synthesize the design. Quartus has these types of rules checks built in.
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2.Does the dedicated clock input pins use the BANK supplies where they are located? I now connect the LVDS(2.5V) clock to the clock input pins of the bank with 1.5v bank supply for DDR3, I am not sure whether this is correct.
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Again, allow Quartus to answer the question; assign an LVDS clock within that bank and see if it is accepted. I'm pretty sure it will, on earlier devices the LVDS input buffer power source was different than VCCIO, so you could have LVDS clock inputs.
Cheers,
Dave
Honored Contributor
