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Altera_Forum's avatar
Altera_Forum
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15 years ago

DDR2 Read Issue in Cyclone III

I've instantiated a DDR2 SDRAM HPC using a Cyclone III. We've simulated the design and it works as expected. Using the hardware and SignalTap, I can do a write, and see the data on the mem_dq lines. When I do a read, I see the data come back on the mem_dq lines but the data is never on the local_rdata(255:0) bus. I believe the Quartus II version is 9.1. We are also using the half-data rate version. The DDR2 SDRAM is a PC-5300, 4GB Micron SO-DIMM. I'm thinking that I have a DDR2 controller issue. We are passing calibration because the ctl_cal_sucess line is high and local_init_done goes high after that.

Any thoughts? Any one else seeing this?

Thanks!

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello dtschindel,

    I would like to ask you if you could solve this problem. If yes, How did you solve it?

    I am having the same situation.

    local_rdata = zero

    Thanks in advance,

    Juan
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Juan,

    We could never get the Altera DDR2 Controller to work. We ended up writing our own DDR2 Controller for the Cyclone III.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello dtschindel,

    ...about the simulation and the local_rdata bus.

    In my case I didn't see any data because I was forgetting to use the memory model in the Quartus II settings.

    After I added the simulation model together with the test_bench file, I could see the local_rdata working.

    Maybe is interesting for you.

    Regards,

    Juan
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hallo,

    I am writing again to update my last comment.

    What I wrote previously is valid for:

    <variation name>_example_top_tb.vhd

    <variation name>_mem_model.vhd

    However, I was trying use my own test bench just using the memory model. Then It did not work.

    Apparently the solution to this is to modify the _example_top_tb.vhd and integrate it with your design. Or read carefully this testbench and add all the memory parameters for the functional simulation.

    Right now I am testing and at least there is result from the local_rdata bus in simulation. However, it is not stable. After few microseconds it is now showing any result.

    I am a bit confused with this simulation. However there must be a solution.

    Regards,

    Juan
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I can think of two possibilities for those 'X':[list][*]you have a second driver in your testbench that forces a different value for local_rdata[*]you are reading an address that hasn't been initialized[/list]Do you have any error message or warning in the Modelsim console?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Dear Daixiwen,

    Thanks for your reply.

    I have tried both.

    1. I added by hand all the necessary files (from the memory controller ip core) and made sure that no other driver was interfering.

    2. About the reading addresses. I am simply incrementing the address by 2. The address has this format: BANK-ROW-COL

    I would like to ask you for a further explanation of the address initialization. Maybe I still don't have this clear.

    In the Modelsim console I only get warning messages.

    Regards,

    Juan
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I forgot to write something,

    I get an error after a while that stops the simulation.

    This is the error:

    # ** Failure: --- Data could not be written, increase array depth or use full memory model ---

    I have tried to change the memory_model to the full_memory_model but is not working. Is not even compiling.

    Regards,

    Juan