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Altera_Forum
Honored Contributor
15 years agoDDR2 Read Issue in Cyclone III
I've instantiated a DDR2 SDRAM HPC using a Cyclone III. We've simulated the design and it works as expected. Using the hardware and SignalTap, I can do a write, and see the data on the mem_dq lines...
Altera_Forum
Honored Contributor
13 years agoHello dtschindel,
I would like to ask you if you could solve this problem. If yes, How did you solve it? I am having the same situation. local_rdata = zero Thanks in advance, Juan