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Altera_Forum
Honored Contributor
Honored ContributorDDR2 Read Issue in Cyclone III
I've instantiated a DDR2 SDRAM HPC using a Cyclone III. We've simulated the design and it works as expected. Using the hardware and SignalTap, I can do a write, and see the data on the mem_dq lines...
Altera_ForumHonored Contributor
Honored ContributorJuan,
We could never get the Altera DDR2 Controller to work. We ended up writing our own DDR2 Controller for the Cyclone III.
