Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

DDR2 Read Issue in Cyclone III

I've instantiated a DDR2 SDRAM HPC using a Cyclone III. We've simulated the design and it works as expected. Using the hardware and SignalTap, I can do a write, and see the data on the mem_dq lines...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hello dtschindel,

...about the simulation and the local_rdata bus.

In my case I didn't see any data because I was forgetting to use the memory model in the Quartus II settings.

After I added the simulation model together with the test_bench file, I could see the local_rdata working.

Maybe is interesting for you.

Regards,

Juan