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Altera_Forum
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15 years ago

DDR2 Read Issue in Cyclone III

I've instantiated a DDR2 SDRAM HPC using a Cyclone III. We've simulated the design and it works as expected. Using the hardware and SignalTap, I can do a write, and see the data on the mem_dq lines...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I forgot to write something,

I get an error after a while that stops the simulation.

This is the error:

# ** Failure: --- Data could not be written, increase array depth or use full memory model ---

I have tried to change the memory_model to the full_memory_model but is not working. Is not even compiling.

Regards,

Juan