DDR2 Read Issue in Cyclone III

Hallo,

I am writing again to update my last comment.

What I wrote previously is valid for:

<variation name>_example_top_tb.vhd

<variation name>_mem_model.vhd

However, I was trying use my own test bench just using the memory model. Then It did not work.

Apparently the solution to this is to modify the _example_top_tb.vhd and integrate it with your design. Or read carefully this testbench and add all the memory parameters for the functional simulation.

Right now I am testing and at least there is result from the local_rdata bus in simulation. However, it is not stable. After few microseconds it is now showing any result.

I am a bit confused with this simulation. However there must be a solution.

Regards,

Juan