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Altera_Forum
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15 years ago

DDR2 Read Issue in Cyclone III

I've instantiated a DDR2 SDRAM HPC using a Cyclone III. We've simulated the design and it works as expected. Using the hardware and SignalTap, I can do a write, and see the data on the mem_dq lines...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Dear Daixiwen,

Thanks for your reply.

I have tried both.

1. I added by hand all the necessary files (from the memory controller ip core) and made sure that no other driver was interfering.

2. About the reading addresses. I am simply incrementing the address by 2. The address has this format: BANK-ROW-COL

I would like to ask you for a further explanation of the address initialization. Maybe I still don't have this clear.

In the Modelsim console I only get warning messages.

Regards,

Juan