Data arrival Path in timing analyser

Hi sstrell,

Thank you for your help!

The first-bit adder is actually assigned myself using set_location_assignment (...)

These names actually matche the one in post-fit technology map, which I have attached for your references.

However, timing analyser shows that the data arrival path is not the same as the one in technology map viewer. If as you mentioned, they are just names, then the name in timing analyser indeed matches the one in technology map viewer and the one in .qsf file.

May I ask what is "location column"? Did you mean the resource property editor, or something else?

Thanks!

Mingqiang

Hi KhaiY,

Thank you for your help!

I have already changed the design by adding flip-flops at the output of each adder.

Now Timing Analyser shows the path is correct.

However, real tests suggest that both Timing Analyser and chip planner does not tell the truth.

It looks like combinatorial adder can never be routed appropriately. I will probably abandon this design.

However, I can still sure the file for your reference. The problem is honestly strange!

Best Wishes,

Mingqiang

Hi KhaiY,

Thank you for your method.

I guess the simulation you refer to is the gate-level simulation.

I had done RTL-level one before and the output sof the adder were correct.

I tried gate level simulation, but it did not give me any timing information about the cascaded length delay. I thus abandoned it.

I would double check the functionality simulation at this level latter. Nevertheless, since I will get an oscilloscope today, it is worth measuring the outputs to see the exact waveforms.

Thank you still for your concern! I will update what I found with you!

Best Wishes,

Mingqiang

Hi KhaiY,

Continuing from the gate-level simulation using Modelsim.

All ouptuts of the adders are correct as expected.

However, I still doubt whether gate-level simulation gives us correct functions in the real chip, though it is reliable to some extent.

I would use oscilloscope to do actual tests to find out what exactly has happened!

Thank you!

Mingqiang

Hi KhaiY,

I feel sorry to not response to you in time as I was so busy doing the experiment that I missed some of the messages previously.

Updating my situation: I used an oscilloscope to debug the adder, finding that neither Timing Analyser and chip planner tells the truth.

There was 30-bit adder connected when I implemented 32-bit adder.

Now I have found ways of solving the problem by removing all adders' inputs away. Instead, I connected these adders' inputs with a 10-bit switch.

Encoding the 10-bits to the number of input bits to adders, I have successfully cascaded a 96-bit adder and measured its delay time.

However, when I cascade more than 128-bit adders, testbench suggested that they may not be cascaded successfully. I am also currently finding out reasons and doing experiments.

It seems that the Quartus compiler connects adders in a very strange way between the inputs and the outputs.

What I do is probably very rare in FPGA and hence many bugs must be found via experiments.

Thank you very much for your concern! You can probably close this topic and label it solved.

Best Wishes,

Mingqiang