Data arrival Path in timing analyser

Hi KhaiY,

Thank you for your method.

I guess the simulation you refer to is the gate-level simulation.

I had done RTL-level one before and the output sof the adder were correct.

I tried gate level simulation, but it did not give me any timing information about the cascaded length delay. I thus abandoned it.

I would double check the functionality simulation at this level latter. Nevertheless, since I will get an oscilloscope today, it is worth measuring the outputs to see the exact waveforms.

Thank you still for your concern! I will update what I found with you!

Best Wishes,

Mingqiang

Hi KhaiY,

Continuing from the gate-level simulation using Modelsim.

All ouptuts of the adders are correct as expected.

However, I still doubt whether gate-level simulation gives us correct functions in the real chip, though it is reliable to some extent.

I would use oscilloscope to do actual tests to find out what exactly has happened!

Thank you!

Mingqiang