Occasional Contributor
Regular ContributorHi,
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Best regards,
KhaiY
Occasional ContributorHi KhaiY,
I feel sorry to not response to you in time as I was so busy doing the experiment that I missed some of the messages previously.
Updating my situation: I used an oscilloscope to debug the adder, finding that neither Timing Analyser and chip planner tells the truth.
There was 30-bit adder connected when I implemented 32-bit adder.
Now I have found ways of solving the problem by removing all adders' inputs away. Instead, I connected these adders' inputs with a 10-bit switch.
Encoding the 10-bits to the number of input bits to adders, I have successfully cascaded a 96-bit adder and measured its delay time.
However, when I cascade more than 128-bit adders, testbench suggested that they may not be cascaded successfully. I am also currently finding out reasons and doing experiments.
It seems that the Quartus compiler connects adders in a very strange way between the inputs and the outputs.
What I do is probably very rare in FPGA and hence many bugs must be found via experiments.
Thank you very much for your concern! You can probably close this topic and label it solved.
Best Wishes,
Mingqiang
