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cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Data arrival Path in timing analyser

Hi everyone, I just came across a very confusing thing about data arrival path in timing analyser. This path mismatched the actual routing path in the chip planner. I placed a 20-bit adder betwee...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Mingqiang,


Can you share the design.qar for investigation?


Thanks.

Best regards,

KhaiY


cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi KhaiY,

Thank you for your help!

I have already changed the design by adding flip-flops at the output of each adder.

Now Timing Analyser shows the path is correct.

However, real tests suggest that both Timing Analyser and chip planner does not tell the truth.

It looks like combinatorial adder can never be routed appropriately. I will probably abandon this design.

However, I can still sure the file for your reference. The problem is honestly strange!

Best Wishes,

Mingqiang

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Mingqiang,

    I tried to locate all the sout in Chip Planner, all are located in 2 LABs.

    Thanks.

    Best regards,

    KhaiY

    • cosx's avatar
      cosx
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi KhaiY,

      Thank you for your help!

      I did what you gave previously by putting them to two LABs, but the adders were still not fully connected. Let me explain this in a bit more detailed way.

      The whole system is actually a testbench that tests the adders' combinatorial delay.

      The one I gave you is a 30-bit adder which delayed certain amount.

      I next cascaded a 20-bit one, with its first 10 bits constraining to the lower half of the first block and the next 10 bits constraining to the upper half of the second one.

      However, this 20-bit adder delayed almost the same as the 30-bit one, meaning that some of the adders were not actually cascaded in the chain, although Timing Analyser said they were.

      I also did another experiment that connected all adders' outputs to the HEX and LED displays on the DE1-SOC board. By setting one of the inputs of the adder 29'h1FFF_FFFF and another one to {29'h0, input}. If the "input" is 1, we will see only last LED is on and all the rest outputs goes to 0.

      Unfortunately, the displayed pattern did not go as expected, meaning that the some of adders were not cascaded properly.

      I will use oscilloscope to test them latter to find out whether the route goes wrong or something else goes wrong.

      If you have the same DE1 board, maybe you can implement the my design on board to test if the delay is correct.

      Thank you still for your help!

      Best Wishes

      Mingqiang