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cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Data arrival Path in timing analyser

Hi everyone, I just came across a very confusing thing about data arrival path in timing analyser. This path mismatched the actual routing path in the chip planner. I placed a 20-bit adder betwee...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Mingqiang,


Can you try to simulate the design and see if the signals give expected result?


Thanks.

Best regards,

KhaiY


cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi KhaiY,

Continuing from the gate-level simulation using Modelsim.

All ouptuts of the adders are correct as expected.

However, I still doubt whether gate-level simulation gives us correct functions in the real chip, though it is reliable to some extent.

I would use oscilloscope to do actual tests to find out what exactly has happened!

Thank you!

Mingqiang