Cyclone V SoC - Shared Memory Controller

Update:

Now the preloader runs through and also configures the brgmodrst correctly.

But I'm not able to read data from FPGA out of the DDR!

Any hints about the settings to be done in the bsp? Or regarding the QSYS-System. Maybe there is s.th. wrong.

If someone is interested I could post also the QSYS-View of the System...

I will try that! (I was using the 13.0 [no SP])

Thanks

That was it.

I made the same steps with SP1 and it works... =)

Thank you!

Hi BadOmen, thank you for this hint.

Do you have an overview of issues for the SoC?

If you are deep in the "SoC-World" maybe you could answer my question how to build a working preloader and uboot?!

My problem for now is that the generated preloader.ds and uboot.ds won't work properly in the DS-5 debugging plattform, are there any issues known or something like a stepbystep-manual?

FYI: I was at the Arrow SoC-Workshop and made my preloader with this steps:

-open embedded command shell

-type bsp-editor to generate the spl-bsp

-type make

-open ds-5 and generate a debugger

-start the preloader.ds

but that don't work...

Hi Taz1984,

I have very similar problem with preloader built procedure under 13.0 SP1 (which was not experienced with former 13.0 version without sp1).

As a workaround I use the makefile which was generated by the BSP 13.0 version.

AS I examined, the problem arise from the missing global variable parameter ( $SOCFPGA_BOARD := socfpga_cyclone5 ), when I compared the makefile 13.0 to the makefile 13.0 SP1 verisons.

Note: use the embedded command shell, for running both 'bsp-editor', and 'eclipse' (= DS5).

This embedded shell stores environment variables which may necessary for compiling and building your design.

Regards,

ZS.V.

Hi again,

I know only one official ' stepbystep-manual' for ARM DS5 Altera Edition (EDS-SOC)

browse for 'ug_soc_eds.pdf'

As a reference design you can examine Golden HW/SW reference design for Cyclone V SoC board.

browse for 'ug_soc_gsrd.pdf'

I hope it will help

Regards,

Zs.V

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What version of the tools are you using? There was an issue that was identified that would cause the transactions to never complete. This occurred when the memory was accessed directly via the FPGA-to-SDRAM interface. I believe this has been corrected in 13.0 SP1.

--- Quote End ---

Dear BadOmen,

As I have seen, you have a lot of valuable answers in the topic of Cyclone V SoC Development kit on the Altera Forum and on the rocketboards.org.

I will describe here my achievements and the problems:

-About 3-4 month ago I am working with Cyclone V Soc boards (formerly revA, now rev.C ES board).

FPGA portion usage:

-I have managed to reach and test the DDR3 memory region clearly within FPGA portion by a Nios II soft core, and a video-test works in 1080p. Nios II can reach and test/validate the memory in soft mode.

HPS portion usage:

-I have managed to reach and test the DDR3 memory region within HPS portion: ARM cores can reach and test/validate the memory in HPC mode. I modified the design from Nios II generated SimpleMemoryTEst template to ARM application processor, by using SOCAL-HWLib level of functions.

- Mixed mode usage: based on Golden SW/HW reference I can easily reach different GPIOs via LW HPS2FPGA bridge by using SOCAL-HWLib level of functions.

.

However, I have the following problems with mixed mode memory accesses (I intended to use HWLib level at first):

- How I can reach FPGA's DDR3 memory / internal BRAM from ARM side (when I set HPS2FPGA bridge)?

- How I can reach HPS' DDR3 memory from FPGA/Nios II side (when I set FPGA2HPS bridge)?

- Are there any reference design for such a mixed mode data transfers between HPS and FPGA portions by using DMA and without DMA conrtoller?

Unfortunately, still I cannot get any valuable response about this topic from Altera SRs.

Thank your for your answer in advance.

Best regards,

Zs.V.