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Altera_Forum
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12 years ago

Cyclone V SoC - Shared Memory Controller

Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi Taz1984,

I have very similar problem with preloader built procedure under 13.0 SP1 (which was not experienced with former 13.0 version without sp1).

As a workaround I use the makefile which was generated by the BSP 13.0 version.

AS I examined, the problem arise from the missing global variable parameter ( $SOCFPGA_BOARD := socfpga_cyclone5 ), when I compared the makefile 13.0 to the makefile 13.0 SP1 verisons.

Note: use the embedded command shell, for running both 'bsp-editor', and 'eclipse' (= DS5).

This embedded shell stores environment variables which may necessary for compiling and building your design.

Regards,

ZS.V.