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What version of the tools are you using? There was an issue that was identified that would cause the transactions to never complete. This occurred when the memory was accessed directly via the FPGA-to-SDRAM interface. I believe this has been corrected in 13.0 SP1.
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Dear BadOmen,
As I have seen, you have a lot of valuable answers in the topic of Cyclone V SoC Development kit on the Altera Forum and on the rocketboards.org.
I will describe here my achievements and the problems:
-About 3-4 month ago I am working with Cyclone V Soc boards (formerly revA, now rev.C ES board).
FPGA portion usage:
-I have managed to reach and test the DDR3 memory region clearly within FPGA portion by a Nios II soft core, and a video-test works in 1080p. Nios II can reach and test/validate the memory in soft mode.
HPS portion usage:
-I have managed to reach and test the DDR3 memory region within HPS portion: ARM cores can reach and test/validate the memory in HPC mode. I modified the design from Nios II generated SimpleMemoryTEst template to ARM application processor, by using SOCAL-HWLib level of functions.
- Mixed mode usage: based on Golden SW/HW reference I can easily reach different GPIOs via LW HPS2FPGA bridge by using SOCAL-HWLib level of functions.
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However, I have the following problems with mixed mode memory accesses (I intended to use HWLib level at first):
- How I can reach FPGA's DDR3 memory / internal BRAM from ARM side (when I set HPS2FPGA bridge)?
- How I can reach HPS' DDR3 memory from FPGA/Nios II side (when I set FPGA2HPS bridge)?
- Are there any reference design for such a mixed mode data transfers between HPS and FPGA portions by using DMA and without DMA conrtoller?
Unfortunately, still I cannot get any valuable response about this topic from Altera SRs.
Thank your for your answer in advance.
Best regards,
Zs.V.
Honored Contributor
