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Altera_Forum
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12 years ago

Cyclone V SoC - Shared Memory Controller

Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

What version of the tools are you using? There was an issue that was identified that would cause the transactions to never complete. This occurred when the memory was accessed directly via the FPGA-to-SDRAM interface. I believe this has been corrected in 13.0 SP1.