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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone V SoC - Shared Memory Controller

Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Update:

Now the preloader runs through and also configures the brgmodrst correctly.

But I'm not able to read data from FPGA out of the DDR!

Any hints about the settings to be done in the bsp? Or regarding the QSYS-System. Maybe there is s.th. wrong.

If someone is interested I could post also the QSYS-View of the System...