Forum Discussion
ContributorCyclone V custom board VCCIO puzzling behavior
Dear Intel and all,
I am working on Cyclone V soc 5CSEBA5U19C8N.
There is a very puzzling VCCIO behavior.
According to "Cyclone® V Device Family Pin Connection Guidelines
PCG-01014-3.2".
Any 3.0 below VCCIO must use a VCCPD with 2.5V.
I am supplying VCCIO of bank 3B+4A with VCCPD 2.5V and the VCCIO is using 1.2V.
However when measuring the VCCIO rail the voltage raised to almost 1.5V.
Before the FPGA chip is applied the voltage rail is able to measure clean 1.2V which eliminates the DCDC issue.
This is very puzzling, please FAE or Intel employee support.
Thank you
There are new measured data.
If I attached a simple 10k resistor to the 1.2V rail. it will drop back to normal 1.2 range.
But the loaded /w 10k is still measuring 40mV higher than unloaded DCDC w/o the FPGA chip.
So there are some leakage current inside the diode path? from VCCPD to VCCIO?
23 Replies
Farabi_AlteraRegular Contributor
Hello,
I am taking over this case from previous owner.
How many devices you see the similar behavior?
This could possibly caused by VCCPD to VCCIO leakage current.
Do you have any undriven IOs with weak pullups?
Please make sure no VCCIO rails unconnected/unused especially FMC slots.
Can use pulldown resistors to stabilize the voltage.
regards,
Farabi
BrianSune_FroumThank you, finally there is FAE or staff can handle this ticket.
1) All
2a) for a development board form factor how could you expect all slot MUST used in any situations?
So of cause the situation happens on FMC slots is not used.
2b) As mentioned even setting this cannot see the effect is removed.So this control on the EDA is so puzzling for what purpose?
3) as mentioned in this very beginning of this ticket, the adjustable DCDC buck converter is tested w/o the FPGA is applied and no voltage raised or out-off-range measurements are found. This is introduced by the FPGA Chip itself.### add ups
** if configurated the unused pins to ground + output.
tested the pins do load to ground.However, the power rails shows very low different 10-5mV different yet still raised a lot from 1.2 to 1.47.
Bests,Brian
- Farabi_Altera
Hello,
1- You observed voltage increase at VCCIO power rails. How about the IO signals within the impacted VCCIO banks? Do you observed voltage increase as well?
2- Do this observation impacted any functional behavior of the device? like design failure, FPGA temperature increase etc?
regards,
Farabi
- BrianSune_Froum
1) yes both VCCIO and the FPGA-IO on the victim banks. However the VCCIO is higher than IO about 20-40mV.
2) Design failure <- not fully understand, temperature increase (cannot tells because w/o HPS running the system total power is less than 1.3W)
If needed can run a IR image to check hot spot but don't think this is helpful due to ~100mA on 12V input.
The design had individual power rail voltage+current sense yet minimum current range is ~=0.217 mA .1mA is measured and print on linux hwmon, not sure this is out of range. (no extra load resistor is added as well)
Extra info:
Currently the DCDC is set to 1.8V no extra resistor or load show no issue.
So it is happened on 1.5V or below VCCIO standard.
- BrianSune_Froum
Any data on the leakage and what is root causes of such leakage?
Thank you - Farabi_Altera
Hello,
Let me check with internal team.
rgards,
Farabi
- BrianSune_Froum
Please do investigate with internal and provide solution and possible causes on such behavior.
This ensure other designer and user should know what VCCPD and VCCIO could be supported.
Bests,
Brian
- Farabi_Altera
Hello,
I have filed investigation request to engineering: 15018404392
This will take some time but engineering will take a look into this.
regards,
Farabi
- BrianSune_Froum
This will help to check how much leakage and possible hazard.
BTW the compile settings make unused IO to output still introduce such problem.
The previous responses are included as much experiment data as possible.
