Honored ContributorIs there anyway in Altera or Verilog code such that the counter gets reset to zero only on power ON. Please advise.
(I am using EP2C35F672C6 "Cyclone II" within DE2 board)
Honored Contributorwhat do you actually mean? Please give some more details.
Honored ContributorRegisters have a power on reset state, it can be defined e.g. as an initial value in VHDL signal definition.
Honored ContributorHonored ContributorI'm not so familiar with Verilog, but Quartus should infer register power-up reset from Verilog initial block:
initial
begin
outcnt<=8'h00;
endThe register will have the power up condition as stated in the verilog design.
I found some instructions on how it can be done different in the quartus help :// Use a variable declaration assignment to set the power-up level
// of an inferred register.
reg q = 1'b1;
always@(posedge clk)
begin
q <= d;
end
reg q;
always@(posedge clk or posedge reset)
begin
if (reset)
q <= 0;
else
q <= d;
endI think, a power-up condition different from asynchronous reset doesn't make much sense. However, from hardware description, I expect that both options exist independantly. In some cases, the power-up level is ignored during synthesis, but you get a warning then.
It could be that the asynchronous reset input is triggered unintenionally at power-up. You can use an asynchronous input gated somehow with another signal to see, if the power-up level is still ignored. According to Verilog IEEE standard, the variable declaration assignment you used should be equivalent to assignment in an initial block.Honored ContributorYou are right if you say it makes no sense to have a different behaviour.
I think most fpga's does not get 'reset' in the sense that you electrically pull a pin up or down. The 'reset' is just part of the configuration process. This way the synthesis of my little example follows the correct path : no difference, and the reset condition is used if any is specified. If howerver, no reset condition is given, you can specify it in an other way, using the initial condition. StefaanHonored ContributorThere is another aspect of power-up level that should be noticed. Quartus II software manual explains how power-up level is achieved:
--- Quote Start --- Registers in the device core always power up to a low (0) logic level on all Altera devices. However, there are ways to implement logic such that registers behave as if they were powering up to a high (1) logic level. --- Quote End --- Depending on the device family, some combinations of asynchronous set/reset and power-up level may be excluded. In this case you get a serious warning, as I mentioned. Also, the (1) power-up level may consume additional logic resources. To my opinion, it's generally useful, to have a hardware reset with FPGA. I sometimes missed it, when it was omitted. An unrelated asynchronous reset may cause undefined behaviour when it is released simultaneously with active clock edge, so it should be better released synchronously. It's easy to combine this circuit with a register or a delay counter that generates a power-on reset also when the hardware reset is missing.Honored ContributorHonored ContributorIt's a "severe warning" that power-up level is ignored. Actually the statement you quoted from my previous post was incorrect, cause power-up level isn't a hardware feature but an option created by the synthesis tool utilizing the fixed low power-up level. For FPGA families not having asynchronous set and reset, the settings may be incompatible as you reported.
