Counter Power on Reset only

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what do you actually mean? Please give some more details.

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A sample code will make me easier to explain:

module myTest(clk,_reset,outcnt);

input clk,_reset;

output reg [7:0] outcnt;

always @(posedge clk or negedge _reset)

begin

if(_reset==1'b0) outcnt<=8'h00;

else outcnt<=out+1'b1;

end

endmodule

Here, _reset is connected to external switch. So, anytime someone pushes that switch, outcnt becomes 8'h00.

But, what I really want to happen is that I want outcnt be zero only at Power ON.

(If I remove _reset signal, what will the initial value of the outcnt at Power ON?)

Is there anyway I can work on DE2 board with Altera 2c35 or Quartus S/W to specify this?

Thanks.