Counter Power on Reset only

The register will have the power up condition as stated in the verilog design.

I found some instructions on how it can be done different in the quartus help :

// Use a variable declaration assignment to set the power-up level
// of an inferred register.
reg q = 1'b1;
always@(posedge clk) 
begin
 q <= d;
end

So it was time to do some tests :

- when a reset condition is specified in the verilog code like this :

reg q;
always@(posedge clk or posedge reset) 
begin
 if (reset)
  q <= 0;
 else
   q <= d;
end

Then the reset condition (q <= 0 ) is used as startup value, regardless the specified initial condition. Even if I set "reg q = 1", the value for the register is zero after configuration.

- when you don't specify a reset condition in the always block, the initial condition specified is used.

However I didn't found a way to visualize the reset condition in the quartus environment (also not in the chip editor).

Stefaan