Counter Power on Reset only

I think, a power-up condition different from asynchronous reset doesn't make much sense. However, from hardware description, I expect that both options exist independantly. In some cases, the power-up level is ignored during synthesis, but you get a warning then.

It could be that the asynchronous reset input is triggered unintenionally at power-up. You can use an asynchronous input gated somehow with another signal to see, if the power-up level is still ignored.

According to Verilog IEEE standard, the variable declaration assignment you used should be equivalent to assignment in an initial block.