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Altera_Forum
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17 years ago

Counter Power on Reset only

Is there anyway in Altera or Verilog code such that the counter gets reset to zero only on power ON. Please advise. (I am using EP2C35F672C6 "Cyclone II" within DE2 board)
Altera_Forum's avatar
Altera_Forum
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17 years ago

Registers have a power on reset state, it can be defined e.g. as an initial value in VHDL signal definition.