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Altera_Forum
Honored Contributor
Honored ContributorCounter Power on Reset only
Is there anyway in Altera or Verilog code such that the counter gets reset to zero only on power ON. Please advise. (I am using EP2C35F672C6 "Cyclone II" within DE2 board)
Altera_ForumHonored Contributor
Honored ContributorI'm not so familiar with Verilog, but Quartus should infer register power-up reset from Verilog initial block:
initial
begin
outcnt<=8'h00;
end
