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Altera_Forum
Honored Contributor
Honored ContributorCounter Power on Reset only
Is there anyway in Altera or Verilog code such that the counter gets reset to zero only on power ON. Please advise. (I am using EP2C35F672C6 "Cyclone II" within DE2 board)
Altera_ForumHonored Contributor
Honored ContributorIt's a "severe warning" that power-up level is ignored. Actually the statement you quoted from my previous post was incorrect, cause power-up level isn't a hardware feature but an option created by the synthesis tool utilizing the fixed low power-up level. For FPGA families not having asynchronous set and reset, the settings may be incompatible as you reported.
