Counter Power on Reset only

You are right if you say it makes no sense to have a different behaviour.

I think most fpga's does not get 'reset' in the sense that you electrically pull a pin up or down. The 'reset' is just part of the configuration process.

This way the synthesis of my little example follows the correct path : no difference, and the reset condition is used if any is specified. If howerver, no reset condition is given, you can specify it in an other way, using the initial condition.

Stefaan