Counter Power on Reset only

There is another aspect of power-up level that should be noticed. Quartus II software manual explains how power-up level is achieved:

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Registers in the device core always power up to a low (0) logic level on all Altera devices. However, there are ways to implement logic such that registers behave as if they were powering up to a high (1) logic level.

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Depending on the device family, some combinations of asynchronous set/reset and power-up level may be excluded. In this case you get a serious warning, as I mentioned. Also, the (1) power-up level may consume additional logic resources.

To my opinion, it's generally useful, to have a hardware reset with FPGA. I sometimes missed it, when it was omitted. An unrelated asynchronous reset may cause undefined behaviour when it is released simultaneously with active clock edge, so it should be better released synchronously. It's easy to combine this circuit with a register or a delay counter that generates a power-on reset also when the hardware reset is missing.