Forum Discussion
Honored Contributorconfig fpgas with other fpga in AS mode
When I config FPGAs with other FPGA in AS mode,I met troubles below.
When I select 3.3v LVTTL as IO STANDARD,the phenomenon is as below. FPGA-1 : the DCLK pin's voltage is about 3.3v FPGA-2 : the DCLK pin's voltage is below 0.6v When I select 2.5v as IO STANDARD(All pins) and set current strength 16MA(config pins only),the phenomenon is as below. FPGA-1 : the DCLK pin's voltage is about 2.5v FPGA-2 : the DCLK pin's voltage is about 2.5v Why the 3.3v LVTTL can not pull the DCLK pin's voltage up to 3.3v? the circuit diagram is attached.10 Replies
Altera_ForumAltera is restricting the current strength with 3.3 and 3.0 V VCCIO for CIII, I guess, it's mostly for reducing signal overshoot. But you probably can damage the FPGA when shorting the output at high current strength.
- Altera_Forum--- Quote Start --- I think, DCLK should achieve full level with 2.5 and 3.3 V standard as well, because the pin is only capacitively loded. --- Quote End --- I also think so,but.... I will do test at other boards to watch the result. besides this,I want to know whether there is any damage to the circuit If I select 2.5v Standard and 16mA current strength(the VCCIO = 3.3v),for that,until now,the main FPGA works normally at FPGAs configuration.
- Altera_Forum
I think, DCLK should achieve full level with 2.5 and 3.3 V standard as well, because the pin is only capacitively loded.
- Altera_Forum--- Quote Start --- These settings can't explain the findings in post# 1 if everything is in regular operation. There must be a kind of hardware error, e.g. other signals shorted to the said DCLK signal that doesn't achieve the full level. --- Quote End --- If as you said,I think the DCLK signal also cann't achieve the full level when 2.5v IO Standard.Can the DCLK signal?
- Altera_Forum
These settings can't explain the findings in post# 1 if everything is in regular operation. There must be a kind of hardware error, e.g. other signals shorted to the said DCLK signal that doesn't achieve the full level.
- Altera_Forum--- Quote Start --- But if you don't connect DATA0 (EPCS data output) at the master FPGA, you aren't able to verify the EPCS programming or check for busy state during programming. Referring to the origibal problem, I presume that you are pulling nCE high during EPCS access? --- Quote End --- I had pull nCE high and nCONFIG low during EPCS access. the VCCIO is 3.3v,and I set IO Standard to be 2.5v.does it matter? the Max current strength is also diffrent between 2.5v IO Standard and 3.3v IO Standard. (3.3v -> Max current strength = 8mA;2.5v -> Max current strength = 16mA)
- Altera_Forum
But if you don't connect DATA0 (EPCS data output) at the master FPGA, you aren't able to verify the EPCS programming or check for busy state during programming.
Referring to the origibal problem, I presume that you are pulling nCE high during EPCS access? - Altera_Forum
new circuit diagram is attached.and the DAT0 is added this time.
- Altera_Forum--- Quote Start --- It's unclear what you are trying to achive.In the shown circuit, it's not possible to configure the slave FPGAs by the master FPGA directly, only writing the EPCS would be an option. But the circuit is apparently incomplete, DAT0 is missing. --- Quote End --- Yes,you are right.I just want to achive FPGAs to be configed by writing EPCS.And also,the DAT0 was not draw.In fact,the DAT0 exists.But,the master FPGA don't need it,so i did not draw it.
- Altera_Forum
It's unclear what you are trying to achive.In the shown circuit, it's not possible to configure the slave FPGAs by the master FPGA directly, only writing the EPCS would be an option. But the circuit is apparently incomplete, DAT0 is missing.
